VTT’s integration team is performing research in the field of advanced interconnects. The long term goal is to establish “via-last” copper Through Silicon Vias (TSV) for different device wafers and vertically stack these devices (i.e. combining vertical and planar interconnects on wafer-level). The beauty of the 3D integration scheme is to vertically integrate devices together to improve the performance, packaging density and to shrink the overall size of the devices.
Flip chip process: The specialty of the team is the solder microbump-based flip chip process. This technology has been widely used for integrating hybrid pixel detectors for high-energy physics and medical applications where the highly segmented bump pads of radiation sensors and an electronics chips are connected with solder bumps.
Electroplating: Thin film deposition of the seed layer is typically done using sputtering. The electroplating is done on wafer level through photoresist mask for 4”-8” wafers and the metals comprise nickel, copper, gold, tin, indium and tin based alloys. For UBM deposition for single chips, Electroless-Nickel Immersion-Gold (ENIG) has been developed. Electroplated metals are used for flip-chip bonding and wafer level metal bonding.
TSV process: A via-last tapered Cu TSV technology is under development. This technology can be applied to MEMS sensors and CMOS wafers in future to increase the packing density of the devices. In MEMS devices, the TSVs are fabricated through the thin caps of encapsulated MEMS devices. For CMOS wafers, solder bumps are combined with TSVs and eventually the chips will be soldered on chip level to next device level or to PCB. The Cu TSVs can be fabricated with pitch larger than 90 µm.
Tailored substrates: Special substrates are needed for various sensors. Substrate R&D is focused in cavity SOI (C-SOI) and TSV interposer wafers. We also create tailored SOI substrates containing buried layers, such as ALD films, LPCVD poly-Si etc.
Wafer thinning: Thinning of wafers is done using a backgrinding system and Chemical Mechanical Polishing (CMP). In addition, CMP processes for Cu polishing have been developed. We have also spin etching tool for wafer thinning and electrostatic carrier system for thin wafer handling.
Wafer bonding technology: Wafers can be permanently bonded using Si-SiO2 direct bonding at high or low (< 400 °C). Low temperature bonding processes are attractive because they enable bonding of active device wafers. Low-temperature metal bonding processes are developed because of the excellent sealing properties of metal joints. We have also bonded other materials than Si, such as glass, sapphire and fused silica.
- T. Suni, R. L. Puurunen, J. Dekker, H. Kattelus, K. Henttinen: Cavity SOI Wafer with Buried Etch-Stop Layer, WaferBond’11 Conference on Wafer Bonding for Microsystems
- P. Dixit et al., “The application of dry photoresists in fabricating cost-effective tapered through-silicon vias and redistribution lines in a single step”, J. Micromech. Microeng. 21 (2011) 025020 (11pp)
- A. Gädda et al., “Electroless Nickel and Immersion Gold deposition on Single Chips for Flip Chip Assembly of Pixel Detectors”, The IMAPS Nordic Annual Conference Proceedings, 2011.
- Hannele Heikkinen et al., “Low-Temperature Bump Bonding of Timepix Readout Chips and CdTe Sensors at Different Sensor Pitches”, 18th International Workshop on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors proceedings, 2011.
Senior Scientist, Team Leader
Tel: +358 40 552 3384
E-mail: Sami.Vahanen [at] vtt [dot] fi